Field-effect transistor and method for manufacturing the field effect transistor

ABSTRACT

A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer. Impurity concentration N 2  and thickness D of the second conductivity layer are such that the following relationship holds:  
       d   &gt;           2        ɛ   S          φ   S         eN   2         +           2        ɛ   S          V   bi         eN   2              N   1         N   1     +     N   2                             
 
     wherein N 1  is the impurity concentration of the first conductivity epitaxial layer, Ø S , ∈ S  and V bi , are surface potential, dielectric constant and a diffused potential, respectively, of the second conductivity epitaxial layer, and e is an elementary charge of electron. An electrically neutral region is formed in the second conductivity epitaxial layer when no voltage is applied between the gate and the source region, whereby the electrically neutral region functions similarly to the gate of a cascode-connected MOSFET, which improves the breakdown voltage of the FET.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a field-effect transistor and,more particularly, to a field-effect transistor having improved,stabilized off-state breakdown voltage as measured between a gate and adrain, as well as to a method for manufacturing the field-effecttransistor.

[0003] 2. Description of the Related Art

[0004] Breakdown voltage is a parameter that determines a maximum outputpower of a power field-effect transistor (power FET). According to aknown method for designing the breakdown voltage of a silicon MOSFET, inwhich a lightly-doped drain (LDD) region existing between a gate and adrain is regarded a junction FET, the device is considered to have astructure such that a MOSFET and the junction FET are cascode-connected.This idea enables the following design practice for an n-type MOSFET,for example. By adjustment of the dosage of n-type ions implanted intothe LDD region existing between a gate and a drain and adjustment of theimpurity concentration of a p-type substrate, it becomes possible toarbitrarily choose a design ratio of the voltage applied between thegate and the drain to the voltage applied between the source and thedrain. Thus, the on-state breakdown voltage between the source and thedrain can be accurately controlled. This technique is described inProceedings of the 6th Conference on Solid State Devices, p249.

[0005] For high power microwave FETs used, for example, in base stationsfor mobile communications and satellite communications, gallium arsenide(hereinafter abbreviated as GaAs) MESFETs and GaAs heterojunction FETs(HJFETs) have been employed. In contrast to the case of MOSFETs that usea gate insulating film, in these GaAs FETs, a Schottky metal of a gate(hereinafter referred to as a gate metal) exhibits a lower Zenerbreakdown voltage. Thus, in addition to improvement of off-statebreakdown voltage, the on-state breakdown voltage between the gate andthe drain must be improved.

[0006]FIG. 1 shows a conventional FET in section. According to a knownmethod for improving the on-state breakdown voltage of a GaAs MESFET, anintentionally undoped i-GaAs layer (numeral 44 in FIG. 1) is formed as asurface layer of the FET which is in Schottky contact with the gate.This structure improves the maximum reverse breakdown voltage of thegate metal; specifically, the on-state breakdown voltage of the FET is20 V or higher. This technique is described in IEICE Transactions, Vol.E74, No. 12, 1991.

[0007] As an alternative technique, there is widely used an LDDstructure in which the impurity concentration of the region existingbetween a gate and a drain is made lower than that of an ohmic region,as in the case of a MOSFET. In this structure, since the impurityconcentration in the vicinity of the gate is lower than that of theohmic region, electric-field concentration at a gate surface isalleviated. This technique is described in The 17th GaAs IC Symposium,1995, Technical Digest. By adjustment of the length of the LDD region, abreakdown voltage of 25 V or higher is obtained.

[0008] The conventional techniques as described above have provided someadvantages, but cannot necessarily exert complete control over theon-state breakdown voltage of GaAs FETs to obtain both the highbreakdown voltages. This is because, in the case of GaAs, a high surfacestate density exists on the surface of a semiconductor, and the surfacestate density have a great effect on the on-state breakdown voltage,whereas the properties of the surface state density depend on the typeof a film and the filming process thereof and are thus difficult tocontrol. In short, the on-state breakdown voltage varies greatly withuncertain factors in a fabrication process, causing frequent occurrenceof breakdown defect during fabrication.

[0009] Since, in many cases, GaAs FETs employ an epitaxial wafer inwhich semiconductor layers are grown in the vertical direction, a dopingprofile cannot be varied parallel to the substrate surface. Thus,application of a cascode connection to a design for a breakdown voltagecontrol as in the case of a silicon MOSFET is difficult in the GaAs FET.Even if an LDD structure is formed in an ordinary GaAs FET by means ofion implantation, the on-state breakdown voltage of the FET is difficultto control, because, in the GaAs FET, dosage of the substrate is usuallynot controlled for this purpose, and thus, the electric potential of thesurface state is unstable.

SUMMARY OF THE INVENTION

[0010] In view of the above, it is an object of the present invention toprovide a field effect transistor having an improved, stable on-statebreakdown voltage between gate and source thereof.

[0011] It is another object of the present invention to provide aprocess for fabricating the field effect transistor as mentioned above.

[0012] The present invention provides a field effect transistorincluding a substrate, a first epitaxial layer overlying the substrateand having a first conductivity, a second epitaxial layer formed on thefirst epitaxial layer and having a second conductivity, source and drainregions in ohmic contact with the second epitaxial layer, and a gatemetal formed on the second epitaxial layer in Schottky contacttherewith, the second epitaxial layer having an impurity concentrationand a thickness such that an electrically neutral region is formed whenthe gate metal has a potential substantially equal to a potential of thedrain region.

[0013] The present invention also provides a method for fabricating afield effect transistor including the steps of depositing a firstepitaxial layer having a first conductivity and overlying a substrate,depositing a second epitaxial layer having a second conductivity on thefirst epitaxial layer, forming an ohmic layer on the second epitaxiallayer, forming an ohmic layer having a first conductivity on the secondepitaxial layer, forming a gate in Schottky contact with the secondepitaxial layer and source and drain regions on the ohmic layer, andselectively etching the second epitaxial layer to form an opening forexposing a portion of the first epitaxial layer by using an etchant, theetchant and a semiconductor material of the epitaxial layer beingselected such that an etch rate of the second epitaxial layer is lowerthan an etch rate of the ohmic layer.

[0014] In accordance with the field effect transistor of the presentinvention and fabricated by the method of the present invention, theelectrically neutral region functions similarly to the gate of thecascode-connected MOSFET, which improves both the on-state breakdownvoltage in the FET.

[0015] The above and other objects, features and advantages of thepresent invention will be more apparent from the following description,referring to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a sectional view of a conventional FET;

[0017]FIG. 2 is a sectional view of an FET according to a firstembodiment of the present invention;

[0018]FIGS. 3A to 3H are sectional views illustrating consecutive stepsin fabricating the FET of the first embodiment;

[0019]FIG. 4 is a graph showing potential change and carrierconcentration distribution along line A-A′ of FIG. 2;

[0020]FIG. 5 is a diagram showing widths of depletion layers in thefirst embodiment;

[0021]FIG. 6 is an equivalent circuit diagram showing operation of theFET of the first embodiment;

[0022]FIG. 7 is a graph showing the operational principle of theinvention;

[0023]FIG. 8 is a sectional view of an FET according to a secondembodiment of the present invention;

[0024]FIG. 9 is a sectional view of an FET according to a thirdembodiment of the present invention;

[0025]FIG. 10 is a sectional view of an FET according to a fourthembodiment of the present invention;

[0026]FIG. 11 is a sectional view of an FET according to a fifthembodiment of the present invention;

[0027]FIG. 12 is a sectional view of an FET according to a sixthembodiment of the present invention;

[0028]FIG. 13 is a sectional view of an FET according to a seventhembodiment of the present invention;

[0029]FIG. 14 is a sectional view of an FET according to an eighthembodiment of the present invention;

[0030]FIG. 15 is a sectional view of an FET according to a ninthembodiment of the present invention; and

[0031]FIG. 16 is a graph illustrating the effect of an FET of thepresent invention with respect to the on-state breakdown voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Now, the present invention is more specifically described withreference to accompanying drawings, wherein similar constituent elementsare designated by similar reference numerals throughout the drawings.

[0033] Referring to FIG. 2, a GaAs MESFET according to a firstembodiment of the present invention includes a semi-insulating GaAssubstrate 11 and the following layers formed sequentially on thesubstrate 11: a buffer layer 12; an n-GaAs channel layer 13 (dosed at2×10¹⁷ cm⁻³, and 235-nm thick); a p-GaAs layer 14 (2×10¹⁸ cm⁻³, 40 nm);an n-GaAs ohmic layer 15 (5×10¹⁷ cm⁻³, 100 nm); an ohmic metal(Au/Ge/Ni) 16 serving as a source and a drain; and a gate metal (WSi/Au)17 serving as a gate. The gate metal penetrates the p-GaAs layer 14 toreach the n-GaAs layer 13 to be in electric contact therewith.

[0034]FIGS. 3A to 3H illustrate the steps of fabricating the MESFET ofthe present embodiment. As shown in FIG. 3A, a semiconductor crystallinewafer having epitaxial layers 14 and 15 is formed by a molecular beamepitaxial (MBE) method; a photoresist 18 is applied onto the crystallinewafer; and the wafer is subjected to exposure and patterning to therebyform an opening in the photoresist 18 at a position corresponding to arecess-to-be of the FET. Next, the n-GaAs ohmic layer 15 doped with Siat 5×10¹⁷ cm⁻³ and having a thickness of 100 nm is removed by etching soas to expose the p-GaAs layer 14 doped with Be at 2×10¹⁸ cm⁻³ and havinga thickness of 40 nm. The etching process may be performed by use of aphosphoric acid etchant and under time control so as to expose thep-GaAs layer 14. In order to improve etching accuracy, GaAs/AlGaAsselective etching is more preferred. In the present embodiment, thewafer is subjected to a wet selective etching by use of an aqueoussolution which contains 50% citric acid and 30% hydrogen peroxide at aratio of 3:1 by volume. After exposing an n-Al_(0.3)Ga_(0.7)As layer 52having a thickness of 5 nm and serving as an etch stop layer, the etchstop layer 52 is etched by means of hydrochloric acid for a short periodof time so as to expose the p-GaAs layer 14.

[0035] Next, as shown in FIG. 3B, a SiO₂ film 19 serving as a mask fordry etching is formed to a thickness of 700 nm over the entirety of theFET. A WSi film 20A serving as a mask for dry etching is deposited onthe film 19 by sputtering. As shown in FIG. 3C, a photoresist is appliedonto the mask WSi film 20A to form a photoresist film 82 having anopening at a position corresponding to the gate-to-be. The mask WSi film20A is removed through the opening by a magnetron ion etching (MIE)method. Then, the SiO₂ film 19 is selectively removed through theopening by a reactive ion etching (RIE) method.

[0036] As shown in FIG. 3D, after the photoresist 82 is removed, theSiO₂ film 19 is selectively etched at the opening by a less-damaging MIEmethod so as to expose through the opening the p-GaAs layer 14. As shownin FIG. 3E, by using a phosphoric acid based etchant, the p-GaAs layer14 is removed through the opening, and the n-GaAs channel layer 13 isetched through the opening to a depth of 20 nm. Next, a gate metal WSi20 is deposited on the entire surface of the FET by sputtering. As shownin FIG. 3F, in order to decrease the gate resistance, a gate metal Au 21is deposited by evaporation, and the deposited gate metal Au 21 isformed into a desired gate shape by an ion milling method. As shown inFIG. 3G, a portion of the SiO₂ film 19 located under the gate is removedby using hydrofluoric acid. As shown in FIG. 3H, a regular surfaceprotection film (SiO₂) 22 is formed, and the ohmic metal (Au/Ge/Ni) 16is formed. A wiring process follows to complete the FET of the presentembodiment.

[0037]FIG. 4 shows potential distribution and carrier concentrationdistribution along line A-A′ of FIG. 2. On the p-GaAs layer 14, holesare accumulated to form an electrically neutral region. Herein, anepitaxial layer is designed such that the concentration N₂ of the secondconductive semiconductor layer and the thickness d of the secondconductive semiconductor layer satisfy the following relationship:$d > {\sqrt{\frac{2ɛ_{S}\varphi_{S}}{{eN}_{2}}} + \sqrt{\frac{2ɛ_{S}V_{bi}}{{eN}_{2}}\frac{N_{1}}{N_{1} + N_{2}}}}$

[0038] where

[0039] N₁ is the impurity concentration of a first conductivity-typeactive layer in contact with a second conductive-type semiconductorlayer,

[0040] Ø_(s) is the surface potential of the second semiconductor layer,

[0041] ∈_(s) is the dielectric constant,

[0042] V_(bi) is the diffusion potential, and

[0043] e is an elementary charge of electron.

[0044]FIG. 5 shows the widths of depletion layers in detail. W₁ denotesthe width of a surface depletion layer and corresponds to the first termof the above expression. W₂ denotes the width of a depletion layerlocated on the channel layer side and corresponds to the second term ofthe above expression. With Ø_(s)=0.7 V, V_(b1)=0.8 V, and N₁=2×10¹⁷cm⁻³, the requirement d>30 nm is obtained for N₂=2×10¹⁸ cm⁻³. Herein,d=40 nm is employed.

[0045]FIG. 6 shows an equivalent circuit diagram illustrating the actionof the present invention. The gate metal (WSi/Au) 17 is considered tohave properties close to those of a p-type material; thus, the gate, thesurface p-GaAs layer, and the drain form a p-p-n junction (gate/(surfacep-GaAs layer)/drain). In this case, when a voltage is applied betweenthe gate and the drain such that the gate potential is negative withrespect to the drain potential, a reverse bias voltage is applied to thep-n junction between the surface p-GaAs layer and the drain. As aresult, the p-GaAs layer 14 begins to become depleted of currentcarriers from the drain side. By contrast, in the p-GaAs layer 14, aneutral region still remains on the gate side. This structure isrepresented by the equivalent circuit in which an equivalent FET 42 iscascode-connected to an equivalent diode 72 of the gate. The neutralizedp-GaAs layer corresponds to the gate region of this FET. The electricpotential V_(G2) of the p-GaAs layer 14 is substantially equivalent tothe electric potential V_(G1) of the gate.

[0046]FIG. 7 shows a graph illustrating the operation of the equivalentcircuit. The abscissa of the graph represents an electric potentialV_(X) at the node connecting the equivalent diode 72 and the equivalentFET 42. The intersection of the Zener breakdown characteristic curve ofa Schottky diode and the source follower characteristic curve of theequivalent FET 42 represents current that flows between the gate and thedrain. A voltage at which current flow starts in the source followercharacteristic is represented by the difference (V_(G2)−V_(T2)) betweenthe gate voltage V_(G2) and the threshold voltage V_(T2) of theequivalent FET 42. A portion, V₁, of the voltage applied between thegate and the drain is applied to the Schottky diode, whereas a portion,V₂, of the voltage is applied to the FET. The maximum reverse breakdownvoltage of the gate metal depends on the semiconductor material andimpurity concentration; thus, in order to maintain a high breakdownvoltage, the difference “V_(G2)−V_(T2)” must be controlled such that V₁is small enough to prevent an excessive bias voltage from being appliedto the Schottky diode.

[0047] In the conventional FET, the surface state density of asemiconductor plays a role of the gate of the equivalent FET 42. In thecase where the surface state density exhibits a hole trap which is aptto capture holes, the electric potential V_(G2) of the surface stateapproaches the electric potential of the gate; thus, the breakdownvoltage is maintained at a certain high level. By contrast, in the casewhere the surface state density exhibits an electron trap which is aptto capture electrons, the electric potential V_(G2) approaches a drainvoltage V_(D); consequently, a bias voltage is applied to the Schottkydiode, resulting in reduction in the breakdown voltage. As mentionedpreviously, these properties of the surface state are generallydifficult to control; thus, stabilization of the breakdown voltage isdifficult.

[0048] By contrast, according to the present invention, since the p-GaAslayer is specifically formed as a surface layer of the FET, the gatepotential V_(G2) of the FET can be controlled without direct influenceof the surface state density. In this case, the thickness of the p-GaAslayer is designed larger than the sum of the thickness of the surfacedepletion layer and the thickness of the depletion layer formed on thechannel side. The p-GaAs layer is also expected to absorb holes, whichare generated by collision ionization and cause reduction in thebreakdown voltage. Thus, according to the present invention, a highbreakdown voltage can be stably maintained.

[0049]FIG. 8 shows a field-effect transistor according to a secondembodiment of the present invention. The FET of the present embodimentincludes a semi-insulating GaAs substrate 11 and the following layersformed sequentially on the substrate 11: a buffer layer 12; a235-nm-thick n-GaAs channel layer 13 doped with Si at 2×10¹⁷ cm⁻³; a40-nm-thick Al_(0.3)Ga_(0.7)As (p-GaAs) layer 14 doped with C at 2×10¹⁸cm⁻³; and a 100-nm-thick n-GaAs ohmic layer 15 doped with Si at 5×10¹⁷cm⁻³. By employment of Al_(0.3)Ga_(0.7)As as the p-GaAs layer 14, in astep equivalent to FIG. 3A, the p-GaAs layer 14 itself plays a role ofetch stopper. Accordingly, the etch stop layer 52 is unnecessary in thepresent embodiment, thereby simplifying the fabrication process.

[0050]FIG. 9 shows a field-effect transistor according to a thirdembodiment of the present invention. The FET of the present embodimentis similar to the first embodiment of FIG. 2 in the arrangement ofepitaxial layers except that the gate metal WSi 17 is formed such thatits tip does not extend through the p-GaAs layer 14. By employment ofthis structure, the maximum reverse breakdown voltage of the gate metal17 is improved, whereas a high breakdown voltage is maintained by thecascode connection between the gate and the drain.

[0051]FIG. 10 shows a field-effect transistor according to a fourthembodiment of the present invention. The FET of the present embodimentis similar to the first embodiment of FIG. 2 in the arrangement ofepitaxial layers except the following features. The gate metal WSi 17has a step, from which the tip of the gate metal 17 protrudes downwardand extends through the p-GaAs layer 14 such that the step abuts the topsurface of the p-GaAs layer 14 whereas the bottom end of the tip of thegate metal 7 abuts the top surface of the n-GaAs channel layer 13. As aresult, the electrical contact area between the gate-metal 17 and thep-GaAs layer 14 increases. Further, by adjustment of the thickness ofthe p-GaAs layer 14 through which the gate extends, the thresholdvoltage of the FET can be adjusted, thereby expanding the design choice.

[0052]FIG. 11 shows a field-effect transistor according to a fifthembodiment of the present invention. The FET of the present embodimentis similar to the first embodiment of FIG. 2 in the arrangement ofepitaxial layers except that a portion of the p-GaAs layer 14 extendingbetween the source and the gate is removed. During operation of anordinary FET, a high breakdown voltage is generally required onlybetween the gate and the drain, and thus a high voltage is not appliedbetween the source and the gate. Accordingly, the portion of the p-GaAslayer 14 that extends between the source and the gate is not necessary.By removal of the portion of the p-GaAs layer 14, the parasiticcapacitance involved between the gate metal 17 and the p-GaAs layer 14on the source side decreases; thus, an improvement in high-frequencycharacteristics can be expected.

[0053]FIG. 12 shows a field-effect transistor according to a sixthembodiment of the present invention. The FET of the present embodimentis similar to the first embodiment of FIG. 2 in the arrangement ofepitaxial layers except the following features. The p-GaAs layer 14provided between the gate 17 and the drain is in contact with the gatemetal WSi 17 and is not in electrical contact with the n-GaAs ohrniclayer 15 on the drain side. As a result, the electric potential of thep-GaAs layer 14 approaches the electric potential of the gate 17 withoutinfluence of the electric potential of the drain. Accordingly, thecascode-connection in the aforementioned circuit for maintaining a highbreakdown voltage functions more effectively. By designing a length forthe p-GaAs layer 14 in addition to an impurity concentration and athickness of the p-GaAs layer 14, the design choice of the FET can beexpanded.

[0054]FIG. 13 shows a field-effect transistor according to a seventhembodiment of the present invention. The FET of the present embodimentis an example of application of pseudomorohic lattice matching ofAlGaAs/InGaAs to a heterojunction FET (HJFET). The FET of the presentembodiment includes: a semi-insulating GaAs substrate 11; a buffer layer12; a high-purity i-In_(0.15)Ga_(0.85)As channel layer 32 (15 nm); ann-Al_(0.2)Ga_(0.8)As donor layer 33 (35 nm) doped with Si at 2×10¹⁸cm⁻³; an Al_(0.2)Ga_(0.8)As (p-GaAs) layer 14 (40 nm) doped with C at2×10¹⁸ cm⁻³; and a GaAs layer (60 nm) doped with Si at 5×10¹⁸ cm⁻³. Inthis case, breakdown voltage can be also improved as in the case of thefirst embodiment of FIG. 2.

[0055]FIG. 14 shows a field-effect transistor according to an eighthembodiment of the present invention. The FET of the present embodimentdiffers from that of FIG. 2 in that the n-GaAs ohmic layer 15 is notprovided and that the ohmic metal 16 (AuGeNi) is formed after removal ofthe p-GaAs layer 14. Rapid thermal annealing (RTA) is performed foralloying at 450° C. for 2 minutes. Since the ohmic metal 16 directlypenetrates into the n-GaAs channel layer 13, the use of the p-GaAs layer14 scarcely raises the contact resistance.

[0056]FIG. 15 shows a field-effect transistor according to a ninthembodiment of the present invention. The FET of the present embodimentis similar to the first embodiment of FIG. 2 in the arrangement ofepitaxial layers and in the fabrication process (FIGS. 3A to 3H) exceptthat the n-GaAs ohmic layer 15 is etched to a depth of 50 nm, followedby vapor deposition of the ohmic metal (AuGeNi) 16 on the etchedportion. After deposition of the ohmic metal 16, RTA is performed foralloying at 450° C. for 2 minutes. Since the ohmic metal penetrates intothe n-GaAs channel layer 13, the use of the p-GaAs layer 14 scarcelyraises the contact resistance.

[0057]FIG. 16 shows the effect of the present invention with respect tothe on-state breakdown voltage in the field-effect transistor. The graphof FIG. 16 shows the gate current of a GaAs MESFET having a gate widthof 100 μm as measured when a voltage is applied between the gate and thesource of the MESFET such that the gate potential is negative withrespect to the source potential. Usually, a voltage at which a currentof 1 mA/mm flows is defined as an on-state breakdown voltage. As seenfrom FIG. 16, the conventional FET exhibits a breakdown voltage of about12 V, whereas, in the FET of the invention, the current does not reach 1mA/mm even when the applied voltage is increased to 25 V, indicating asignificant improvement in the breakdown voltage.

[0058] Since the above embodiments are described only for examples, thepresent invention is not limited to the above embodiments and variousmodifications or alterations can be easily made therefrom by thoseskilled in the art without departing from the scope of the presentinvention.

What is claimed is:
 1. A field effect transistor (FET) comprising asubstrate, a first epitaxial layer overlying said substrate and having afirst conductivity, a second epitaxial layer formed on said firstepitaxial layer and having a second conductivity, source and drainregions in ohmic contact with said second epitaxial layer, and a gatemetal formed on said second epitaxial layer in Schottky contacttherewith, said second epitaxial layer having an impurity concentrationand a thickness such that an electrically neutral region is formed whensaid gate metal has a potential substantially equal to a potential ofsaid drain region.
 2. The FET as defined in claim 1 , wherein said gatemetal has a bottom surface in contact with said second epitaxial layer.3. The FET as defined in claim 1 , wherein said gate metal penetratessaid second epitaxial layer to electrically contact said first epitaxiallayer.
 4. The FET as defined in claim 3 , wherein said gate metal has astep portion from which a tip portion of said gate metal protrudes, saidstep portion has a bottom surface abutting said second epitaxial layer,and said tip portion abuts said first epitaxial layer.
 5. The FET asdefined in claim 1 , wherein said second epitaxial layer has an openingbetween said gate metal and said source region, and said gate metal hasa bottom abutting said first epitaxial layer.
 6. The FET as defined inclaim 1 , wherein said second epitaxial layer has an opening exposing aportion of said first epitaxial layer located between said gateelectrode and said drain region.
 7. The FET as defined in claim 1 ,wherein the following relationship holds:$d > {\sqrt{\frac{2ɛ_{S}\varphi_{S}}{{eN}_{2}}} + \sqrt{\frac{2ɛ_{S}V_{bi}}{{eN}_{2}}\frac{N_{1}}{N_{1} + N_{2}}}}$

wherein N₁ is an impurity concentration of said first epitaxial layer,wherein Ø_(S), ∈_(S) V_(bi), N2 and d are surface potential, dielectricconstant, a diffused potential, an impurity concentration and thickness,respectively, of said second epitaxial layer, and wherein e is anelementary charge of electron.
 8. A method for fabricating a fieldeffect transistor comprising the steps of depositing a first epitaxiallayer having a first conductivity and overlying a substrate, depositinga second epitaxial layer having a second conductivity on said firstepitaxial layer, forming an ohmic layer on said second epitaxial layer,forming an ohmic layer having a first conductivity on said secondepitaxial layer, forming a gate in Schottky contact with said secondepitaxial layer and source and drain regions on said ohmic layer, andselectively etching said second epitaxial layer to form an opening forexposing a portion of said first epitaxial layer by using an etchant,said etchant and a semiconductor material of said epitaxial layer beingselected such that an etch rate of said second epitaxial layer is lowerthan an etch rate of said ohmic layer.
 9. The method as defined in claim8 , further comprising the steps of selectively etching portions of saidohmic layer corresponding to said source and drain regions and fillingsaid etched portions with an ohmic metal.